1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, to a semiconductor device having a contact with a small leakage current at a portion near a channel stopper immediately below a field oxide film serving as an element isolation region, and a method of manufacturing the same.
2. Description of the Prior Art
With advances in the miniaturization of integrated circuit devices formed in semiconductor substrates, demands have arisen for micropatterning and higher integration of elements. As a result, it is also required that the distance between elements, i.e., the width of a field oxide film serving as an element isolation region, be 0.5 .mu.m or less. As the element isolation region decreases in size, the isolation function deteriorates. As a result, a punch-through phenomenon occurs between elements to cause leakage of a current. As a conventional means for solving this problem, a method of forming an impurity region having the same conductivity type as a semiconductor substrate immediately below the field oxide film, and increasing the impurity concentration of only this portion of the substrate has been used. FIGS. 1A to 1E show a conventional device using this method. FIGS. 1A to 1E are sectional views showing the steps in manufacturing a dynamic RAM cell constituted by a MOS capacitor and a MOS transistor.
As shown in FIG. 1A, a 500-nm thick field oxide film 2 serving as an element isolation region is formed on a p-type semiconductor substrate 1 by a known method. More specifically, this region is formed by a so-called LOCOS method or the like in which an element formation region is masked with an oxidation-resistant mask member, e.g., a silicon nitride film, and thermal oxidation is performed while only the element formation region is exposed. A p.sup.+ -type channel stopper 3 is formed immediately below the element isolation region to prevent the above punch-through phenomenon, i.e., current leakage between elements. This stopper may be formed by implanting phosphorus ions into a field oxide film formation region by using the above silicon nitride film as a mask before the field oxide film 2 is formed by thermal oxidation. Alternatively, the stopper may be formed by implantation of phosphorus ions, after the formation of the field oxide film 2, while the implantation energy is adjusted such that the ions pass through the field oxide film 2 and exhibit a concentration peak immediately below the field oxide film 2. The field oxide film 2 and the p.sup.+ -type channel stopper 3 are formed by these methods. After a gate oxide film having a thickness of 10 to 15 nm is formed in the element region surrounded by the field oxide film 2, a 200-nm thick n.sup.+ -type polysilicon film is deposited on the resultant structure. The n.sup.+ -type polysilicon film is then etched by a known photolithographic technique to pattern a gate electrode 9 (word line). After the gate electrode 9 and the field oxide film 2 are masked, phosphorus ions are implanted at a dose of 3.times.10.sup.13 cm.sup.-2 to form n-type diffusion layers 4. The junction depth of these n-type diffusion layers 4 is set to be about 0.07 .mu.m. The n-type diffusion layers 4 serve as the source and drain regions of a MOS transistor.
For example, a 500-nm thick silicon oxide film serving as an insulating film 5 is deposited on the resultant structure. Thereafter, as shown in FIG. 1B, a contact portion 6 is formed by using a photoresist (not shown) as a mask to reach the n-type diffusion layer 4. As shown in FIG. 1C, n-type polysilicon is deposited on the insulating film 5 and the contact portion 6, and is patterned to form a storage electrode on the contact portion 6, thereby forming a storage electrode 10 of a capacitor. The resultant structure is then annealed to thermally diffuse the impurity from the storage electrode 10 consisting of n-type polysilicon into the p-type semiconductor substrate 1, in which the n-type diffusion layers 4 are formed, through the contact portion 6, thereby forming an n.sup.+ -type diffusion layer 11, as shown in FIG. 1D. Note that the n-type storage electrode 10 may be formed by depositing undoped polysilicon, patterning it, and diffusing an impurity such as phosphorus. If this method is used, the n.sup.+ -type diffusion layer 11 is formed at the same time phosphorus as an impurity is diffused. After this step, as shown in FIG. 1E, a capacitance insulating film 13 having a thickness of 3 to 5 nm (as a silicon oxide film) is formed on the upper and side surfaces of the storage electrode 10, and a plate electrode 14 is formed by using a 200-nm thick n-type polysilicon film. The capacitance portion of a dynamic RAM cell is formed in the above manner. When a wiring layer (not shown) serving as a bit line is formed on this structure, a dynamic RAM cell is completed. The capacitance portion is formed by the above method to have a structure in which the n-type diffusion layer 4 and the n.sup.+ -type diffusion layer 11 are integrated into an n.sup.+ -type diffusion layer 20. The charge stored in the storage electrode 10 is transferred from the n.sup.+ -type diffusion layer 20 to the n-type diffusion layer 4 upon ON/OFF operation of the gate electrode 9 of the MOS transistor, thus inputting/outputting data.
In the case of the contact having the arrangement described with reference to the above conventional device, the n.sup.+ -type diffusion layer 20 is formed near the field oxide film 2 with advances in the micropatterning of elements. For this reason, the n.sup.+ -type diffusion layer 20 contacts the p.sup.+ -type channel stopper 3, and a p.sup.+-n.sup.+ junction portion 21 is formed therebetween. FIG. 2 shows the impurity concentration profile of the p.sup.+ -n.sup.+ junction portion 21. The profile of the p.sup.+ -type channel stopper 3 exhibits a concentration peak at a depth of about 0.11 .mu.m and a concentration of about 5.times.10.sup.17 cm.sup.-3. In contrast to this, the profile of the n.sup.+ -type diffusion layer 20 exhibits a concentration peak at the substrate surface and a concentration of about 5.times.10.sup.18 cm.sup.-3. As shown in FIG. 2, therefore, the p.sup.+ -n.sup.+ junction portion 21 is formed at a depth of about 0.08 to 0.09 .mu.m. However, neither of the p.sup.+ - and n.sup.+ -type impurity concentrations of the p.sup.+ -n.sup.+ junction portion 21 are peak values. That is, the p.sup.+ -n.sup.+ junction portion 21 is formed at a depth where the impurity concentrations are insufficient. As a result, when a potential is applied to the p.sup.+ -n.sup.+ junction portion 21, a depletion layer extends to both the p.sup.+ - and n.sup.+ -type impurity sides. If the depletion layer extends to the n.sup.+ -type impurity side, in particular, a G-R center (generation and recombination center) in the n.sup.+ -type diffusion layer 20 enters the extended depletion layer. The resultant layer serves as a leak path, so that the stored charge leaks to the substrate side. If the amount of the impurity diffused from the storage electrode 10 is increased to compensate for the concentration of the p.sup.+ -type channel stopper 3 so as to prevent this leakage of charge, the n.sup.+ -type diffusion layer 20 spreads in not only the direction of depth but also the lateral direction. As a result, the distance from another adjacent n.sup.+ -type diffusion layer decreases. Consequently, the withstand voltage between the n.sup.+ -type diffusion layers decreases, and leakage of charge occurs.